You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 9 Next »

<UPDATE WITH SAME LAYOUT AS ERICSSON LAB DETAIL PAGE>

Unicycle OVS-DPDK Validation Servers

HP

ProLiant DL380 Gen10

Dual socket Intel(R) Xeon(R) Gold 6152 CPU @ 2.10GHz

384GB RAM

Storage

                HPE Smart Array P816i-a SR Gen10

6x2.4GB (Bay 1-6),

4x480GB SSD (Bay 7-10)

PCI-E Cards:

PCI-E Slot 1          Empty slot 1

PCI-E Slot 2          HPE 12G SAS Expander Card

PCI-E Slot 3          Intel(R) Ethernet Controller XXV710 for 25GbE SFP28

PCI-E Slot 4          Empty slot 4

PCI-E Slot 5          Intel(R) Ethernet Controller XXV710 for 25GbE SFP28

PCI-E Slot 6          HPE Ethernet 10Gb 2-port 562SFP+ Adapter


Dell

<INSERT DIAGRAM WITH SPECIFIC NIC SLOTS>

Unicycle SR-IOV Validation Networking

The diagram below shows the physical and L2 connectivity, the IP subnet plan, host and iDRAC/iLO addressing used in the validation.

The Rover deployment does not configure the networking subsystem thus the choice of switch subsystem components is not restricted to those shown and they can be replaced with devices offering equivalent functionality.


Unicycle SR-IOV Validation IP/VLAN Plan



Unicycle OVS-DPDK BGP Plan

The three unicycle nodes automatically peer with an external fabric BGP speaker using eBGP. The calico nodes do not peer using an internal iBGP mesh.


Unicycle SR-IOV LAG Details



  • No labels